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4.5.2
Synchronous Double Sample Rate Mode
The device can be programmed to respond in Synchronous Double Sample Rate Mode with minimum latency by setting the
TRANS_MD[1:0] bits to “Synchronous Double Sample Rate Mode”. The LATENCY bit does not affect operation in this mode.
In Synchronous Double Sample Rate Mode, the most recent interpolated acceleration data sample is latched at the time pro-
grammed in TIMESLOTA[9:0], relative to t TRIG (rising edge of Sync Pulse). This data is transmitted starting at the time pro-
grammed in TIMESLOTA[9:0], relative to t TRIG . In addition, the most recent interpolated acceleration data sample is latched at
the time programmed in TIMESLOTB[9:0], relative to t TRIG (rising edge of Sync Pulse) This data is transmitted starting at the time
programmed in TIMESLOTB[9:0], relative to t TRIG .
When Synchronous Double Sample Rate Mode is enabled, PSI5 Initialization data is transmitted in both TIMESLOTA[9:0] and
TIMESLOTB[9:0]. Identical data is transmitted in both Time slots, including the 10-bit resolution Raw Offset and Self-Test Data
in Field 9, D27 though D31 if enabled.
≤ t LAT_INTERP +t DATASETUP_double ≤ t LAT_INTERP +t DATASETUP_double
t TIMESLOTA
t TIMESLOTB
Figure 37. Synchronous Double Sample Rate Mode
Note: In the event that the programmed values in TIMESLOTA [9:0] and TIMESLOTB [9:0] result in a conflict, no data will be
transmitted in TIMESLOTB [9:0] .
MMA52xxKW
Sensors
Freescale Semiconductor, Inc.
45
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